KiCad MCP Pro Server

Generate one of two fixed fresh manufacturing snapshots for benchmark evidence.

Compare the two fixed manufacturing snapshot manifests after byte revalidation.

Call this FIRST to store design intent for placement, routing, and gates. v1 parameters (all boards): connector_refs, decoupling_pairs, critical_nets, power_tree_refs, analog_refs, digital_refs, sensor_cluster_refs, required_sheets, optional_sheets, rf_keepout_regions, manufacturer, manufacturer_tier. v2 parameters (professional projects): power_rails (list of PowerRailSpec dicts), interfaces (list of InterfaceSpec dicts), mechanical (MechanicalConstraint dict), compliance (list of ComplianceTarget dicts), cost (CostTarget dict), thermal (ThermalEnvelope dict).

Import structured product/spec text into ProjectDesignIntent conservatively. Accepts JSON or YAML frontmatter/fenced blocks. The importer only persists explicit supported ProjectDesignIntent fields; it reports missing mandatory decisions, placeholders, and extra fields such as MPN/LCSC/populate lists without inventing values. Use ``dry_run=True`` first, then re-run with ``dry_run=False`` after reviewing the parsed result.

Show the persisted project design intent used by placement and release gates.

Return the resolved project design spec with explicit and inferred fields.

Infer a design spec from the active PCB without writing it to disk.

Validate the resolved design spec against the active project PCB.

Generate a professional workflow prompt tailored to the resolved project spec.

Create a child schematic sheet and add it to the active top-level schematic. Optional ``sheet_pins`` is a list of ``[name, type]`` two-element arrays, laid out by the same rules as ``sch_import_sheet_pins``.

Move the hierarchical sheet named ``name`` (its ``Sheetname``) to a new anchor. Only the sheet's ``(at ...)`` anchor and its pins move; each pin keeps its offset and rotation. Size, styling, UUIDs and the child file are untouched.

Remove the hierarchical sheet named ``name`` (its ``Sheetname``) from the parent. Deletes the whole ``(sheet ...)`` block including its instance/path bookkeeping -- the inverse of ``sch_create_sheet``. The child file is left in place. Reports if the name is not found.

Add a hierarchical label, preserving the requested shape and rotation. By default the text is justified away from the directional icon based on ``rotation`` (0=left, 90=bottom, 180=right, 270=top) so it doesn't render on top of the icon. Pass ``justify`` to override, or "none" to force KiCad's centered default.

Add a global label, preserving the requested shape and rotation. By default the text is justified away from the directional icon based on ``rotation`` (0=left, 90=bottom, 180=right, 270=top) so it doesn't render on top of the icon. Pass ``justify`` to override, or "none" to force KiCad's centered default.

Add one hierarchical sheet pin to a sheet symbol at an explicit position. ``position_along_edge`` runs clockwise from the right edge: ``right`` measures from the top, ``bottom`` and ``top`` from the left, and ``left`` from the bottom. Use ``sch_import_sheet_pins`` to derive every pin from the child sheet instead of placing them one by one. Limitations, all deliberate: - The position is used exactly as given. It is **not** snapped to the schematic grid, so a pin placed off-grid will have no wire snap to it. ``sch_import_sheet_pins`` does snap. - A position past the end of an edge is accepted, which puts the pin off the sheet symbol -- ``position_along_edge=1000.0`` on a 20 mm sheet yields y around -949. Nothing warns. - ``top`` and ``bottom`` pins survive here, but ``sch_import_sheet_pins`` only ever places pins on ``left`` and ``right``. A later import relocates a hand-placed top or bottom pin to one of those two edges.

Mirror each child sheet's hierarchical labels as pins on its sheet symbol. This is KiCad's "Import Sheet Pins" without the GUI: without these pins the sheets are electrically separate, ERC reports ``hier_label_mismatch`` for every label, and a net that crosses sheets appears twice in the netlist. Inputs are laid out on the left edge and every other pin type on the right, alphabetically; the sheet symbol grows taller if it must. Every pin of a touched sheet is re-laid-out, including existing ones, because KiCad measures left-edge pins from the bottom -- so a growing sheet would otherwise move them. An existing pin keeps its name and its UUID, and is moved to wherever this layout puts it; its type is changed if the child sheet's label shape now says something else. Pins without a matching label are reported, never deleted. Only the ``left`` and ``right`` edges are used, so a pin hand-placed on ``top`` or ``bottom`` with ``sch_add_sheet_pin`` is relocated. The report counts added, retyped, moved and unchanged pins separately. ``grow_sheet`` (default on) lets the sheet symbol grow to fit its pins: taller for the fuller edge, and wider if the estimated label text of the two columns would collide. The sheet never shrinks and never moves. Width growth uses an estimated text width (heuristic: 1.1 x font height per character), not a measured one, and says so in the report. Turning ``grow_sheet`` off keeps the size fixed, and any sheet whose pins then do not fit is skipped **entirely** -- reported, with nothing written for it -- rather than partially written. A half-pinned sheet is worse than an unchanged one. Leave ``sheet`` empty to process every child sheet. Use ``dry_run`` to see the report without writing.

Move sheet-symbol columns apart to make room for stub-and-label wiring. Sheets are grouped into columns by overlapping x-span, and only whole columns move -- and only to the right, never left and never vertically. Run this **before** ``sch_wire_sheet_pins``, not after: it refuses to move a sheet already wired on a pin, since that would silently disconnect the wire (KiCad joins on exact coordinate equality), and ``sch_wire_sheet_pins`` wires every pin it touches by default. If any sheet that must move has a wired pin, the **whole** spread is refused, not just that sheet's own column, since a partial spread would leave the untouched columns' stub-and-label layout unplanned for. With ``min_gap_mm`` unset, the gap required between two neighboring columns is derived from the pin names that actually face each other across it (the longest right-edge name on the left, the longest left-edge name on the right), plus ``margin_mm``. That per-character width is an *estimate* (1.1 x font height per character), not a measured one, so the margin absorbs noise in the estimate; the report says so whenever the estimate drove a move. Set ``min_gap_mm`` to use a fixed gap instead and skip the estimate entirely. An unrecognized paper size skips the page-edge overflow check -- disclosed as skipped, never guessed. A pin whose ``(at ...)`` node can't be read is left in place and reported, never rewritten blind. Use ``dry_run`` to see the report without writing.

Connect sheet pins by giving each one a wire stub and a local label. A sheet pin alone joins nothing -- two sheets become one net only once something in the parent schematic connects their pins, and matching names are not enough (unlike global labels). This writes a short wire stub out of every sheet pin, then a **local** label carrying the pin's name at the far end. Same-named local labels on one sheet are one net; that is what actually joins the sheets, not the pins themselves, and no wire ever has to route between sheet symbols (crossing wires in KiCad merge geometrically into silent shorts). Run ``sch_spread_sheets`` first, not after: once a pin is wired here, ``sch_spread_sheets`` refuses to move any sheet with a wire on one of its pins, and since this tool wires every pin it touches by default, running it first leaves ``sch_spread_sheets`` nothing it can move. A pin that already has a wire on it is left alone. A pin name that appears on only one sheet symbol is reported rather than silently skipped, because its label would dangle with no matching net to join. Label overlap is judged from an *estimated* text width (1.1 x font height per character), not a measured one, and the report says so whenever that estimate was actually used to decide something. Labels from top- and bottom-edge pins are not checked for overlap at all -- judging a vertical label's text-flow direction correctly would need a live render this tool doesn't have, and a wrong guess would be worse than no check; the report calls this out whenever such a pin exists. ``sheet``, if given, limits which sheet's pins get a *new* stub and label; every sheet's pins still count toward orphan and overlap detection, since a name only "matches" once its counterpart elsewhere in the document is known. Use ``dry_run`` to see the report without writing.

List all schematic symbols, optionally from a child sheet.

List all wires in the schematic, optionally from a child sheet.

List all labels in the schematic, optionally from a child sheet.

List unique net names derived from labels, optionally from a child sheet.

Report native KiCad Populate/DNP status for schematic components. Returns each placed component's ``populated``/``dnp``/``in_bom`` state and any recorded DNP reason. Pass ``reference`` to inspect a single part or ``sheet`` to scope the scan to one schematic file.

Calculate absolute pin positions for a given symbol placement.

Check whether common power nets appear to be flagged.

Set board title block information (KiCad 10.0.1+). Title block fields appear on printed outputs and drawings. Args: title: Board title. date: Board date. revision: Board revision. company: Company name. comment1: Custom comment field 1. comment2: Custom comment field 2. comment3: Custom comment field 3. comment4: Custom comment field 4. Returns: Confirmation message with updated fields.

Snap off-grid symbols, labels, wires, and junctions onto the drawing grid. Off-grid anchors are the top cause of ragged sheets and wires that visibly miss their pins. Symbols translate as a whole so pins stay aligned. Runs as a dry run by default (reports the moves and whether connectivity is preserved); pass apply=true to commit. Apply is refused if it would change any net.

Straighten almost-orthogonal wire segments onto the horizontal/vertical axis. Diagonal wires read as rushed; small off-axis deltas are snapped flat. Dry run by default; apply=true commits, and is refused if a straighten would change connectivity.

Flip the justify of overlapping labels so their text stops colliding. Connectivity-safe by construction: the label anchor never moves, only the rendered text direction. Dry run by default; apply=true commits.

Upright sideways power/ground symbols, rotating about the pin to keep the net. Rotates 90/270-degree power symbols to upright and translates them so the pin stays on its original coordinate. Dry run by default; apply=true commits, and is refused if the net would change.

Normalise outlier font sizes onto the sheet's dominant size. Connectivity-neutral typography cleanup over placed-symbol and label text only (never the library cache). Dry run by default; apply=true commits.

Export Gerber manufacturing files.

Render a 3D view of the active PCB board to a PNG image. Parameters ---------- output_file : str Output file name (PNG or JPG). Defaults to ``render.png``. side : str View direction: ``top``, ``bottom``, ``front``, ``back``, ``left``, ``right``. zoom : float Camera zoom factor (0.05–20.0). width, height : int | None Output image dimensions in pixels. quality : float | None Rendering quality (0.0–1.0). preset : str | None Render preset name (e.g. ``photo``, ``standard``). use_board_stackup_colors : bool Use the board stackup-defined colors. floor : bool Show the reflective floor. Default True. perspective : bool Perspective projection. Set False for orthographic. pan_x, pan_y : float | None Camera pan offset in mm. rotate_x, rotate_y, rotate_z : float | None Camera rotation in degrees. light_top, light_bottom, light_side, light_camera : float | None Light intensity for each direction (0.0–1.0). light_side_elevation : float | None Side light elevation angle in degrees.

Export the schematic BOM using KiCad's Python BOM engine.

Run headless visual/readability QA on the active schematic sheet(s). Detects readability defects ERC cannot — overlapping labels, off-sheet symbols or labels, dense unreadable label fanout, and title-block gaps — directly from the schematic S-expression geometry, with no rendering required. Returns JSON with an overall PASS/WARN/FAIL status and per-sheet findings carrying object refs and positions for follow-up.

Score the active schematic's cosmetic quality on a 0-100 scale. Extends readability QA with the traits that separate a professional sheet from a merely-working one: on-grid placement, orthogonal wiring, consistent typography, upright power/ground symbols, and balanced sheet composition. Returns a deterministic per-sheet and overall score with a per-category penalty breakdown and the worst category to fix first — the loop signal for the visual-excellence workflow. No rendering or live KiCad required.

List configured symbol and footprint libraries.

Search symbol libraries by name, description, or keywords. The query is split into whitespace-separated terms. A symbol matches when EVERY term is found (case-insensitive) in any of its name, description, or keywords (AND across terms, OR across fields). A single-term query behaves as a plain case-insensitive substring match. Parameters ---------- query : str Search terms. Multiple whitespace-separated terms are matched with AND semantics; a single term is a case-insensitive substring match. library_filter : str Optional library name to narrow the search. page : int Page number (1-based). Default 1. page_size : int Results per page. Default 50, max 500.

Return details for a single symbol.

Search footprint libraries by footprint name. Parameters ---------- query : str Search term (case-insensitive substring match). library_filter : str Optional library name to narrow the search. page : int Page number (1-based). Default 1. page_size : int Results per page. Default 50, max 500.

List footprints in a specific library.

Rebuild the in-memory symbol search index.

Return details for a single footprint.

Return the configured 3D model path for a footprint.

Set or replace the 3D model path on a footprint. Parameters ---------- library : str Library name (e.g. ``Package_SO``). footprint : str Footprint name (e.g. ``SOIC-8_3.9x4.9mm_P1.27mm``). model_path : str Absolute or relative 3D model file path (Step, VRML, etc.). offset_xyz : str | None Optional offset as ``"x y z"`` in mm (e.g. ``"0 5 0"``). scale_xyz : str | None Optional scale as ``"x y z"`` (e.g. ``"1 1 1"``). rotate_xyz : str | None Optional rotation as ``"x y z"`` in degrees.

Remove 3D model reference(s) from a footprint. Parameters ---------- library : str Library name. footprint : str Footprint name. model_path : str | None If provided, only remove the model with this exact path. If omitted, all 3D model references are removed.

Bulk-assign a 3D model to multiple footprints matching a pattern. Parameters ---------- library : str Library name. footprint_pattern : str Regex pattern to match footprint names (e.g. ``SOIC.*``, ``QFP.*``). model_path : str 3D model file path to assign to all matched footprints.

Search for available 3D model files in the footprint library directory. Parameters ---------- query : str Search term (case-insensitive, matched against path).

Add a jumper symbol to the schematic.

Renumber schematic references sequentially.

Ask KiCad to reload the active schematic.

Generate an IPC-7351B compliant KiCad footprint (.kicad_mod) and save it. Supported packages: 0201, 0402, 0603, 0805, 1206, 1210, 2512 (chip passives), SOT-23, SOT-223, SOT-89, SOT-363/SOT-26, SC-70/SOT-323, SOD-123, SOD-323, SMA/SMB/SMC (DO-214), DPAK/TO-252, D2PAK/TO-263, SOIC, SOP, SSOP, TSSOP (dual SMD), QFP, LQFP, TQFP (quad flat), QFN, DFN (no-lead), BGA (ball grid array), PinHeader (through-hole). Args: package: Package family name (case-insensitive). density: IPC-7351B density level: A (generous), B (nominal), C (compact). pin_count: Number of leads / balls (required for multi-lead packages). pitch_mm: Lead pitch in mm. body_l_mm: Body length in mm. body_w_mm: Body width in mm (QFP only; defaults to body_l_mm). rows: BGA rows or PinHeader row count (1 or 2). exposed_pad_mm: Exposed pad size for QFN in mm. ball_diameter_mm: BGA ball diameter in mm. output_path: Optional relative path inside output_dir. Defaults to ``footprints/<package>.kicad_mod``. Returns: Confirmation with the saved file path, or an error message.

Validate a two-terminal chip footprint against its IPC-7351B nominal (hard gate). Reads the .kicad_mod at ``footprint_path`` (relative to the project), parses its SMD pads, and compares pad width/height/pitch to the IPC-7351B nominal for the given chip ``size_code`` and ``density``. Gross deviation is a blocking FAIL, minor deviation WARNs, a match PASSes. Scope: chip passives (0201–2512) against the IPC-7351B *standard* nominal — not a datasheet-specific land-pattern check.

Certify a footprint against package, documentation, and standard checks (#201). Reads the .kicad_mod at ``footprint_path`` (relative to the project) and runs package-agnostic certification: pad count vs the package name (SOIC/QFP/QFN/ SOT/DIP…), documentation-layer completeness (courtyard/fab/silkscreen), and the recorded IPC-7351 density. Returns one aggregate PASS/WARN/FAIL with per-check findings; a missing courtyard or too-few pads is a blocking FAIL. Headless — no KiCad IPC. For two-terminal chip *geometry* use lib_validate_footprint_ipc7351.

Route a single straight track segment.

Create a simple orthogonal route between two pads.

Export a Specctra DSN for FreeRouting; may require a one-time KiCad GUI step. Uses headless ``kicad-cli pcb export specctra`` when the CLI supports it. If KiCad cannot export the DSN headlessly, returns a human-gated result describing the File > Export > Specctra DSN step instead of failing opaquely.

Stage a routed Specctra SES and surface the required KiCad GUI import step. KiCad has no headless SES import, so this stages the session and returns a human-gated result: the routing is applied by running File > Import > Specctra Session in the PCB Editor. It never reports the board as routed when it is not (``changed=False``, ``human_gate_required=True``).

Apply a routed Specctra SES to the active board headlessly -- no GUI step. KiCad has no headless SES import, so this parses the routed session and writes its segments and vias directly into the .kicad_pcb via the round-trip-safe S-expression layer; the rest of the board file is untouched. Re-applying the same session is deterministic and idempotent (it replaces, not duplicates, the routing). This closes the manual File > Import > Specctra Session step. Run run_drc() afterwards to verify.

Run FreeRouting after placement, then surface the KiCad import step. DSN export is attempted headlessly; FreeRouting runs via Docker or a local JAR. Applying the routed SES session back to the board has no headless path in KiCad, so this returns a human-gated result (``human_gate_required=True``) describing the File > Import > Specctra Session step — it does not claim the board is routed when the session has only been staged. If headless DSN export is unavailable, the manual export step is surfaced instead of failing opaquely. When the experimental MCP Tasks extension is enabled (``KICAD_MCP_ENABLE_TASKS=1``), the routing runs in the background and a task reference is returned immediately. The caller can poll ``tasks/get`` for completion and ``tasks/cancel`` to abort routing.

Write net-class routing constraints into the active .kicad_dru file.

Write differential-pair routing constraints for a pair of nets.

Write a length-tuning rule and report the current delta for a net.

Create or update a KiCad 10-style time-domain tuning profile.

List configured time-domain tuning profiles.

Assign a named tuning profile to a net or wildcard net group.

Create a KiCad 10-inspired time-domain tuning rule with a length fallback.

Write matched-length rules for both nets in a differential pair.

Generate .kicad_dru rules and net-class constraints from the project design intent. Reads power_rails and interfaces from the stored design intent (project_get_design_spec / import_design_spec) and synthesises: - Minimum trace widths from IPC-2221 current-capacity formula (power rails) - Net-class clearance + width + via rules (per-rail) - Differential-pair skew / length / impedance rules (per interface) - HV creepage/clearance rules for rails above 50 V Run drc_check_rule_conflicts() afterwards to surface any conflicts.

Set schematic title block fields on the root sheet or a child sheet. Unspecified fields are preserved. Use ``sheet`` for a named child sheet or ``sheet_file`` for a specific ``.kicad_sch`` file; omit both to target the active root schematic.

Change the schematic sheet (paper) size. Use this when the current sheet is too small to fit all symbols — for example after ``sch_auto_place_functional`` warns that symbols were placed outside the sheet boundary, or when you receive a screenshot showing components outside the red sheet border. Supported sizes (landscape): A4, A3, A2, A1, A0, A (letter), B, C, D, E, USLetter, USLegal. After resizing you should call ``sch_auto_place_functional`` again so that symbols are re-distributed across the larger sheet. Args: paper: Target paper size keyword (default "A3"). Returns: Confirmation with old and new dimensions.

Automatically grow the sheet to fit all currently placed symbols. Reads the bounding box of all placed symbols and selects the smallest standard paper size (A4 → A3 → A2 → A1) that contains them with the configured margin. If the current sheet already fits, reports that no change is needed. Returns: The chosen paper size and new dimensions, or a message if the current size is already sufficient.

Review GND plane presence and a simple void-risk proxy.

Check EMC return-path continuity for a signal or all critical high-speed nets.

Warn when routed signals share layers with split non-ground planes.

Review whether ICs have nearby decoupling capacitors.

Estimate via-stitching density from existing ground vias.

Review diff-pair skew and width symmetry.

Review a high-speed net class for a short-stub proxy.

Run a lightweight EMC sweep with at least ten heuristic checks.

Toggle KiCad 10 hop-over display in the active project settings.

List candidate pins and units that can participate in a swap workflow.

Record a pin-swap back-annotation intent for a component.

Record a gate-swap back-annotation intent for a multi-unit component.

Return the professional PCB design workflow as a typed phase state machine. Lays out the canonical Planner -> Builder -> Verifier -> Fixer -> Release sequence, with the high-level tool and the quality gates each phase must pass. Pass the phases already finished in ``completed_phases``; the tool marks them COMPLETE, reports the first remaining phase as READY (the current step) with its next action and gates, and flags when a human gate is required. Read-only and headless — use it to drive an autonomous design run step by step.

Run the project quality gate and automatically apply server-side fixes. Each iteration: 1. Evaluates all project quality gates. 2. For **auto-applicable** gates (annotation, zone refill) — calls the underlying fix implementation directly on the server, then re-evaluates. 3. For gates requiring **agent action** — returns the tool name and description so the agent can call it, then the agent must call this tool again to continue. The loop runs up to ``max_iterations`` times applying auto-fixes. It stops early when all gates pass or when no further auto-fix is possible without agent involvement. Args: max_iterations: Maximum number of auto-fix + re-evaluate cycles to attempt before returning control to the agent (1–20).

Run ERC/DRC/project gates in a bounded fix-and-rerun validation loop.

Generate the gated manufacturing release package.

Report how much of KiCad's programmatic surface this server can drive. Answers "can I do X with this server?". Pass ``query`` to search capabilities by keyword or tool name, ``domain`` to list one domain's capabilities, or neither for overall and per-domain coverage plus the biggest open gaps. Coverage % = covered / (total - gui-only-no-api); GUI-only-no-api items are KiCad API limits, not gaps in this server.

Remove a specific wire segment using its UUID or unique UUID prefix.

Remove a placed symbol and any directly attached wire segments.

Delete label(s) (local/global/hierarchical) matching ``name`` at the given coordinate. Use sch_get_labels() to find exact names/positions.

Delete the no-connect marker(s) at the given coordinate. Use sch_get_symbols()/sch_get_connectivity_graph() to find pin positions.

Move the label matching ``name`` at (x_mm, y_mm) to a new coordinate, optionally re-rotating it. snap_to_grid defaults to False so the anchor can land exactly on a pin/wire endpoint.

Set the text justification of an existing label (local/global/ hierarchical) matching ``name`` at (x_mm, y_mm). Use sch_get_labels() to find exact names/positions. Global and hierarchical labels carry a directional icon at their anchor; KiCad centers unjustified text on that anchor, which overlaps the icon. Pass "left", "right", "top", "bottom", or a combination like "left top" to move the text clear of the icon, or "none" to restore KiCad's centered default.

Return persisted quality-gate trend history for one gate.

Generate a comprehensive design-status report. Combines intent summary, v2 spec richness, project gate evaluation, and a prioritised list of next steps into a single structured report. This is the recommended first call after opening a project to understand its current state.

List currently selected items in the PCB editor.

Return the current board as a bounded S-expression string.

List all board nets.

List all board copper zones.

List graphical board shapes.

List board pads.

List enabled board layers.

List every layer referenced by a footprint block, including inner layers.

Headless PCB readability QA: off-board parts, silk and body overlap. A fast, file-backed first pass that runs without a live KiCad: it flags footprints whose body leaves the board outline, reference designators that collide on the silkscreen, and overlapping footprint bodies — directly from the ``.kicad_pcb`` geometry. It complements (does not replace) the authoritative DRC run, which remains the sign-off check for courtyard and silk clipping. Returns JSON with an overall PASS/INFO/WARN status and per-finding refs/positions.

Scope re-validation after an edit: semantic-diff the design intent and report which gates must re-run. Compares a baseline design spec — the declared/saved intent, or an explicit baseline passed as ``baseline_spec_json`` — against the intent inferred from the current board, then maps each change to the gates it can invalidate. Re-run only the impacted gates and keep the rest as already-proven. Use after editing an existing project so a small change does not force a full re-validation.

Summarize the current board.

List board tracks.

List board vias.

List board footprints.

Export the PCB to PDF.

Export a bill of materials.

Return the semantic circuit IR for the active schematic. The IR decouples 'what the circuit is' (components, nets, pin roles, power domains, interfaces) from 'how KiCad stores it' (geometry, UUIDs, file format). Wiring is expressed in terms of pin names and roles, not coordinates. The output is a structured text summary of the IR.

List available design variants and basic component counts.

Create a new design variant, optionally cloning an existing variant.

Set the active design variant for the current project.

Override component population, value, or footprint in a variant.

Diff the effective BOM between two design variants.

Export a variant-specific BOM into the project output directory.

Clone an existing design variant under a new name. Parameters ---------- name : str Source variant name. new_name : str Target name for the cloned variant.

Delete a design variant. Parameters ---------- name : str Variant name to delete. Cannot delete the ``default`` variant.

Get the effective status of a single component in a variant. Parameters ---------- variant : str Variant name. reference : str Component reference designator (e.g. ``R1``, ``C4``).

Export a variant-specific schematic PDF with overrides applied. Parameters ---------- variant : str Variant name. output_name : str | None Output filename (defaults to ``<variant>_schematic.pdf``).

Export a manufacturing package for a specific variant. Combines Gerber, drill, BOM, and pick-and-place exports with the variant's overrides applied. Parameters ---------- variant : str Variant name. output_name : str | None Output filename for the package manifest (defaults to ``<variant>_manufacturing.json``).

Get KiCad version information and current connection status.

Search live component sources for purchasable parts. ``source``: ``jlcsearch`` (JLCPCB public catalog, no credentials; default), ``nexar`` (requires NEXAR_CLIENT_ID/NEXAR_CLIENT_SECRET), ``digikey`` (requires DIGIKEY_CLIENT_ID/DIGIKEY_CLIENT_SECRET), or ``mouser`` (requires MOUSER_API_KEY). The authenticated sources are inactive until their credentials are configured (loaded from ``.env`` at server startup). Set ``rohs_compliant`` to ``true`` to filter to RoHS-compliant parts only. ``lifecycle`` filters to a specific lifecycle status (e.g. ``Active``, ``NRND``, ``EOL``) when the provider reports it.

Return live component detail for a specific LCSC code or MPN. Displays sourcing metadata (lifecycle, RoHS compliance) and a datasheet URL when the provider reports them.

Return a structured sourcing policy verdict for one live part.

Assign an LCSC part code to a schematic symbol property.

Generate a live BOM summary with unit and extended pricing.

Check live stock availability by schematic reference or part number. Provide ``refs`` to look up stock for schematic references (resolving each reference to its part number via the active schematic), or ``mpns`` to look up stock directly by manufacturer part number / LCSC code without needing a schematic. This lets you vet a BOM before the schematic exists. Supply at least one of ``refs`` or ``mpns``.

Find nearby alternative parts for the supplied LCSC code.

Check a part choice for reliability derating and approved-vendor (AVL) compliance. Verifies the operating value stays within the derating limit for the component ``kind``/``parameter`` (e.g. capacitor/voltage <= 80% of rated), and — when ``approved_vendors`` is given — that ``manufacturer`` is on the approved-vendor list. Returns one PASS/WARN/FAIL verdict. Derating factors are conservative general-practice values, not a specific MIL/IPC mandate.

Recommend a purchasable part given electrical requirements. Args: category: Component category keyword to search (e.g. "LDO regulator", "N-channel MOSFET", "ferrite bead", "ESD protection"). requirements: Dict of electrical parameter hints used for post-search filtering. Common keys: ``voltage_v``, ``current_a``, ``vgs_v``, ``rds_on_mohm``, ``psrr_db``, ``capacitance_uf``, ``resistance_ohm``. Values can be numbers (min) or ``{"min": x, "max": y}`` dicts. package: Optional SMD package filter (e.g. "SOT-23", "SOIC-8"). only_basic: Prefer JLCPCB basic parts (lower assembly cost). source: Parts source: ``"jlcsearch"``, ``"nexar"``, or ``"digikey"``. max_results: Maximum number of recommendations to return. Returns: Ranked list of part recommendations with LCSC code, MPN, package, price.

Assign a live part (LCSC/MPN) to a schematic symbol and optionally its footprint. This is the recommended tool for closing the part-selection loop after lib_recommend_part() or lib_search_components() returns a suitable part. Args: sym_ref: Schematic reference designator (e.g. "U1", "C4"). lcsc_code_or_mpn: LCSC part code or manufacturer part number. auto_assign_footprint: If True, attempts to assign the footprint from the live part data to the symbol. Requires the schematic backend. source: Parts source for detail lookup. Returns: Confirmation of LCSC/MPN assignment and footprint status.

Return a datasheet URL from the symbol library when available.

Instantiate a subcircuit template — returns a structured action plan. This tool returns a structured plan describing the symbols, connections, and part-search steps needed to add the subcircuit to the schematic. It does NOT directly edit the schematic (use the plan as a guide for calling sch_add_symbol, sch_add_wire, lib_recommend_part, etc.). Args: template_name: Template name (from sch_list_templates()). prefix: Reference prefix applied to all template refs (e.g. ``"PWR_"`` produces ``PWR_U1``, ``PWR_L1``, etc.). params: Dict of parameter overrides (e.g. ``{"vout_v": 5.0}``). Returns: Step-by-step instantiation plan in markdown format.

Preview how netlist-aware schematic compilation will resolve endpoints and wires. Mirrors ``sch_build_circuit``: by default nets resolve to collision-safe terminal stubs; pass ``unsafe_routed_wires=True`` to preview routed Manhattan wire segments instead.

Build (overwrite) the active schematic from structured symbol, wire, and label inputs. IMPORTANT: This tool **replaces** the entire schematic content. Any symbols already placed in the schematic will be lost. To add symbols to an existing schematic without erasing it use ``sch_add_symbol`` / ``sch_add_wire`` / ``sch_add_label`` instead. Coordinates are snapped to the 1.27 mm / 50 mil grid by default. When no coordinates are provided for a symbol, set ``auto_layout=True`` so the placement engine assigns non-overlapping positions automatically. When ``nets`` are provided, the builder is connection-aware. By default it uses the **collision-safe** strategy: each pin endpoint gets a short stub plus a same-named terminal (a global label for signal nets, a power symbol for power nets), so nets connect *by name* and can never short by crossing wire geometry. Nets that cannot resolve to a routable pin endpoint raise a clear error (or are surfaced as warnings) instead of silently producing a disconnected schematic. Each net may set an optional ``scope`` to control the emitted terminal label kind: ``"global"`` (default when omitted, connects across the whole design), ``"local"`` (sheet-local label), or ``"hierarchical"`` (with an optional ``shape`` of input/output/bidirectional for sheet-pin wiring). Set ``unsafe_routed_wires=True`` only if you explicitly want routed Manhattan wire segments between pins. That star-routing can cross unrelated pins or labels and KiCad will merge them by geometry, so it can introduce silent shorts on non-trivial netlists — prefer the default terminal strategy. Each symbol may carry an optional ``properties`` mapping (``dict[str, str]``); every key/value is written verbatim as an additional schematic symbol field, alongside the standard fields — handy for order numbers such as ``{"MPN": "...", "Mouser": "...", "LCSC": "..."}`` without a second ``sch_update_properties`` pass. Keys colliding with the standard Reference/Value/Footprint/Datasheet fields are ignored in favour of the dedicated ``reference``/``value``/``footprint`` inputs (those always win). With ``auto_layout=True`` the placement engine grows the sheet up the ISO-A ladder (A4 → A3 → A2 → A1 → A0) only as far as ``max_paper`` (default ``"A3"``). Once the cap is reached, placement continues on that paper instead of selecting a larger page. This limits paper growth but does not guarantee that arbitrarily dense inputs fit within the capped page; use visual/layout validation or explicit coordinates for dense designs. Pass a larger cap (e.g. ``max_paper="A0"``) for the historical largest-paper behavior. ``max_paper`` must be one of A4/A3/A2/A1/A0; any other value raises ``ValueError``. Recommended workflow: 1. Call ``sch_find_free_placement(count=N)`` to obtain safe coordinates. 2. Pass those coordinates in the ``symbols`` list. 3. OR set ``auto_layout=True`` and omit coordinates entirely.

Set the board origin (drill origin) in millimeters. The origin is used as the reference point for drill files and some export formats. Args: x_mm: X coordinate in millimeters. y_mm: Y coordinate in millimeters. Returns: Confirmation message with new origin coordinates.

Get the current board origin (drill origin) in millimeters. Returns: JSON string with origin coordinates or message if not supported.

Load a bundled manufacturer DFM profile for subsequent checks.

Run a manufacturer-aware DFM review using the active bundled profile.

Estimate fabrication cost from board area, layers, and via count.

Show a concise startup guide and all tool categories.

Re-run only the gates an edit could have invalidated; prove the rest preserved. Computes the semantic intent diff (like ``project_assess_edit_impact``), then actually re-runs only the impacted project gates -- skipping unaffected ones -- so a small edit does not force a full re-validation. Impacted analysis categories that the sign-off gate does not cover (signal integrity, power, thermal, EMC) are listed with the tool to re-run for each.

Set the active KiCad project directory and file paths.

Show the currently configured KiCad project paths.

List known DRC rules from the active ``.kicad_dru`` file.

Report conflicting or unsatisfiable rules in the active ``.kicad_dru``. Flags duplicate rule names (KiCad keeps only the last), two scoped rules setting different minimums for the same constraint and condition, inverted min/max bounds, and negative dimensions. Useful after generating constraints from several sources (net classes, interface binders, manufacturer profiles) to reconcile them to one truth.

Create or update a custom DRC rule in the active ``.kicad_dru`` file.

Delete a custom DRC rule from the active rules file.

Enable or disable a custom DRC rule.

Export the active custom DRC rules file for sharing or CI.

Return full DRC report with PCB violations, unconnected items, and courtyard issues.

Run schematic electrical rule checks.

Run DRC and ERC and summarize readiness.

Evaluate whether the schematic is clean enough to proceed.

Evaluate whether the PCB is physically clean enough to proceed.

Evaluate whether schematic structure and hierarchy look electrically meaningful.

Check the schematic against professional electrical-design rules (advisory). Beyond ERC connectivity: flags supply rails that feed ICs without a decoupling capacitor and I2C buses without pull-up resistors. This is an advisory critic (WARN), not a hard release gate, so it complements ``run_erc()`` rather than replacing it.

Evaluate whether footprint placement is overlap-free and inside the board frame.

Return a structured placement-quality report for capable MCP clients.

Evaluate whether named schematic pad nets transferred cleanly onto PCB pads.

Validate board layer table and stackup copper layer consistency.

Check whether routed tracks still contain non-professional 90-degree corners.

Run the professional release gate bundle before manufacturing handoff.

Score PCB placement quality and explain both hard failures and softer warnings.

Evaluate manufacturing readiness against the active or requested DFM profile.

Run the full project quality gate across schematic, PCB, DFM, and parity checks.

Return the full project gate in structured form for capable MCP clients.

Produce the single manufacturing sign-off report. Binds each declared design-intent requirement to the gate check(s) that would catch a violation, attaches the gate evidence and full provenance (engine versions, rule profile, intent and source hashes), and returns one PASS/FAIL verdict. A board with no declared intent is UNVERIFIED, not a silent PASS. ``export_manufacturing_package`` is hard-gated on the same underlying project gate, so a PASS here means the package will export.

Assemble a release-readiness evidence bundle for human manufacturing review. Aggregates project gate results, DRC/ERC summaries, BOM completeness, waiver state, release artifacts, and manifest presence into one structured, text-renderable payload. Missing required evidence fails closed. When ``output_path`` is provided, the bundle is also written as JSON, Markdown, HTML, or a print-friendly HTML report (``pdf-ready``).

Run a lightweight DFM check using available DRC data.

Return only unconnected DRC issues for focused follow-up after run_drc.

Return only courtyard DRC issues for focused follow-up after run_drc.

Return silkscreen overlap issues from DRC.

Compare PCB footprint references against the schematic symbol references.

Place selected references with a deterministic cluster, linear, star, or grid layout. Unlike the legacy behaviour, this version reads all already-placed symbols first and avoids placing new symbols on top of them. Fixed/already-placed symbols that are not in ``symbol_list`` are treated as immovable obstacles.

Reposition symbol Reference/Value text onto the clearest body side. Mirrors KiCad's ``autoplace_fields``: for each symbol the visible Reference and Value fields are moved to the body side with the most clearance, away from pins and neighbouring symbols, so the rendered sheet stops stacking text on top of other text. Footprint/Datasheet and hidden fields are left untouched. Pass ``references`` to limit the operation to specific designators, or ``dry_run`` to preview the count without writing. Run this after ``sch_auto_place_symbols`` (or any bulk placement) and use ``sch_visual_qa`` to confirm the ``text_overlap`` findings clear.

Iteratively fix schematic readability defects until clean or stable. Runs the headless ``sch_visual_qa`` checks, then applies the matching fixer and re-checks, looping until the sheet passes, no further progress is made, or ``max_passes`` is reached: - **off-sheet** symbols/labels -> grow the sheet one paper size (A4 -> A3 ...) - **text overlap** -> auto-place Reference/Value fields onto clear body sides - **symbol-body overlap** -> re-space the symbols on a body-sized grid, but ONLY when the sheet has no wires, labels or power symbols (moving a connected symbol would break its nets); otherwise it is reported. Dense label clusters are reported for manual follow-up (label anchors are electrical attachment points and cannot be moved safely). Returns a per-pass log with the before/after QA status so the closing state is explicit.

Place schematic symbols into semantically meaningful zones on the sheet. Unlike the basic ``sch_auto_place_symbols`` which uses a plain grid, this tool categorises each symbol by its **function** (MCU, connector, power IC, sensor, passive, protection …) and places it in the corresponding region of the schematic sheet. The result is a readable, professionally structured schematic with logical signal flow (connectors on the left, processing in the centre, power/decoupling at the bottom). Zone layout (column × row, each cell = 25.4 × 17.78 mm):: Col → 0-2 3-5 6-8 Row 0: connectors MCU UI/LED/SW Row 3: power IC sensors/IC protection Row 5: power_pass passives transistors/filter Row 7: test points --- misc The actual sheet size is read from the schematic file. If the symbol count would overflow the current sheet, a warning is appended recommending ``sch_auto_resize_sheet`` to switch to a larger format (A3, A2, …) before re-running this tool. Symbols already placed (not in ``symbol_list``) are treated as fixed obstacles and will not be overwritten. Within each zone, symbols are arranged in a compact row-major sub-grid. Args: symbol_list: Optional list of reference designators to place. If omitted, all symbols in the schematic are placed. anchor_ref: Optional single reference or list of references to keep fixed while re-placing the remaining symbols around them. Returns: A summary showing how many symbols were placed per functional zone, plus an overflow warning if the sheet is too small.

Export the schematic to PDF.

List child sheets from the active top-level schematic.

Return metadata for a specific child sheet.

List the hierarchical sheet pins of one child sheet symbol.

Summarize the active schematic as a textual net connectivity graph.

Trace a named net through the active schematic and matching child sheets.

Show the current stackup.

Set the active board stackup using a file-backed profile.

Export a board layer to SVG when supported.

Export a board layer to DXF when supported.

List board groups (KiCad 10.0.0+). Groups are logical collections of board items that can be moved and manipulated together. Returns: JSON string with group information or message if not supported.

Panelize the active PCB using KiKit. Creates a panel of multiple boards for efficient PCB fabrication. Requires ``kikit`` to be installed (``pip install kikit``). Args: layout: Panel layout type: ``"grid"`` (rectangular array), ``"mousebites"`` (tab+mousebite breakaway), or ``"vcut"`` (V-cut scoring). rows: Number of board rows in the panel. cols: Number of board columns in the panel. spacing_mm: Gap between boards in mm. frame_width_mm: Panel frame/rail width in mm. output_path: Optional output file path (relative to output_dir). Defaults to ``panel/<boardname>_panel_<rows>x<cols>.kicad_pcb``. dry_run: If True, return the planned command and output path without writing files. confirm: Must be True when ``dry_run`` is False to run KiKit. Returns: Confirmation with the panel file path, or an error message.

Generate a bring-up test plan from the project design intent. Produces a structured markdown checklist covering: - Power-on sequence and current limit checks for each power rail. - Protocol loopback / link-up checks for each interface. - Critical-net continuity probes. - Visual inspection items. Args: output_path: Optional relative path for saving the plan (e.g. ``"test_plan.md"``). If omitted, returns the plan as text only. confirm_overwrite: If True, allow overwriting an existing output file. Returns: Bring-up test plan in markdown format.

Generate a SHA256-signed release manifest for the manufacturing package. Collects all files in the output directory, computes SHA256 hashes, and records tool versions, intent hash, and gate status into a ``manifest.json`` and ``MANIFEST.txt``. Args: output_path: Subdirectory inside the project (defaults to ``output/``). Returns: Confirmation with manifest path and file count.

Apply JLCPCB CPL rotation corrections to a KiCad-exported pick-and-place CSV. KiCad exports component orientations relative to its own coordinate system, which differs from what JLCPCB's SMT assembly service expects. This tool reads a CPL CSV (produced by export_pos), applies per-footprint rotation offsets from the bundled ``jlcpcb_rotations.json`` table, and writes a corrected CSV ready for direct upload to JLCPCB. Columns expected (KiCad default CPL export): Ref, Val, Package, PosX, PosY, Rot, Side Args: cpl_csv_path: Path to the CPL CSV file (relative to project dir). output_path: Output path for the corrected CSV. Defaults to ``<stem>_jlcpcb_corrected.csv`` next to the input file. dry_run: If True, return a preview table without writing the file. confirm: Must be True when ``dry_run`` is False and a file will be written. Returns: Summary of corrections applied, or a preview table for dry_run.

Report whether the detected KiCad CLI advertises a given board-import format.

Import a non-KiCad PCB file to KiCad format. Parameters ---------- input_file : str Path to the non-KiCad board file. output_file : str Optional path for the imported KiCad PCB file. format : str Input format: auto, pads, altium, eagle, cadstar, fabmaster, pcad, solidworks. report_format : str Import report format: none, json, text. report_file : str Optional file path for the import report.

Import an Allegro board into a KiCad project directory.

Import a PADS PCB into a KiCad project directory.

Import a gEDA PCB into a KiCad project directory.

Import a Specctra DSN/SES file into a KiCad project directory.

Generate a machine-readable manufacturing release evidence bundle. Runs compliance gates, checks required artifacts, and produces a signed evidence JSON with a ``release_approved`` / ``release_blocked`` verdict. Gates evaluated: - **Artifact coverage**: Gerber, drill, BOM, and pick-and-place files must exist in the output directory. - **DRC gate**: PCB design rule violations must be zero. - **ERC gate**: Schematic electrical rule violations must be zero. - **HV safety gate**: If ``voltage_v`` > 60 V or ``product_domain`` is ``hazardous_mains``, a ``*.kicad_dru`` file with HV creepage rules must exist. Args: output_path: Output directory for the evidence bundle (default: project output/). product_domain: ``"selv"`` (Safety Extra-Low Voltage, ≤ 60 V DC) or ``"hazardous_mains"`` (> 60 V DC, requires HV safety gate). voltage_v: Working voltage in volts; used to auto-select safety domain. waive_missing_artifacts: If True, missing artifact types do not block release. dry_run: Evaluate gates without writing the evidence file. Returns: JSON with ``verdict``, ``gates``, ``blocking_reasons``, and ``evidence_path``.

Verify a placed component's symbol, footprint, and pins actually match. For the given schematic reference designator this checks, entirely from local project files (no network access): - symbol pin count vs footprint connectable pad count - pin numbers vs pad numbers - footprint courtyard / fabrication / silkscreen completeness - 3D model presence (advisory) - datasheet evidence (advisory; never auto-filled) Returns a JSON object with a ``status`` of PASS / WARN / FAIL and a list of per-check ``findings``. FAIL marks a structural contract violation, WARN marks a quality/completeness smell, and INFO is advisory evidence that never changes the overall status.

Poll a safe live schematic preview state and refresh rendered output on changes. This is an opt-in polling watcher for agents and companion-plugin flows. It records the current schematic file signature, debounces rapid writes, then refreshes a PNG preview when the watched files are stable. KiCad GUI reload is deliberately opt-in via ``reload=True`` because the tool cannot reliably prove that the user has no unsaved GUI edits.

Render a schematic sheet to PNG for visual self-checks. Uses headless ``kicad-cli sch export svg`` followed by SVG-to-PNG conversion. Empty sheets return ``status=empty_sheet`` instead of a misleading blank image.

Render the exact visual delta produced by the last schematic mutation. The red pixels are the aligned before/after image difference. Metadata lists every changed symbol, label/net, wire, bus, junction, or document object.

Create a stored schematic change plan from a JSON spec (no write). The spec describes a small subcircuit as ``components`` (reference + lib_id, optional value/footprint) and ``labels`` (text + x/y) plus optional ``nets`` and ``title``. Returns the content-addressed ``plan_id`` to use with the preview/apply/verify/rollback tools.

Return the object changes a plan would make, without writing anything.

Checkpoint the schematic, then apply the plan's net labels. Copies every schematic file into a per-plan checkpoint before mutating, so ``sch_rollback_plan`` can fully restore the prior state. The label insertion runs through the project's atomic, validating writer.

Verify an applied plan: confirm labels exist; report ERC availability. Connectivity verification (that every planned label is present in the schematic) runs file-backed. Full ERC is declared explicitly as available or unavailable rather than silently skipped — run ``run_erc()`` for the full gate.

Restore the schematic from a plan's checkpoint, undoing the apply.

Return statistical data about all nets in the active PCB. Includes per-net counts of tracks, vias, pads, and total track length (mm). Uses an active KiCad IPC connection when available; falls back to file-level net enumeration.

Inspect every detail about a specific net in the PCB. Parameters ---------- net_name : str The exact net name to inspect (e.g. ``GND``, ``+3V3``, ``USB_DP``).

Export drill files.

List all available tool categories and capabilities.

Get tool names in a category, optionally filtered by maturity.

Export the schematic to SVG when supported.

Export the schematic to DXF when supported.

Persist a SPICE directive used by future MCP simulation runs.

Run a DC operating-point analysis.

Run a small-signal AC sweep.

Run a transient time-domain simulation.

Run a DC sweep for an independent source.

Estimate loop crossover and phase margin from an AC sweep.

Assign SPICE model properties to a component in the active schematic. Sets Sim.Name, Sim.Library, Sim.Type, Sim.Pins, and Sim.Params symbol properties. Empty strings are skipped so you can update a single field without overwriting the others.

List SPICE model libraries registered in the active project.

Register a SPICE model library in the active project file. Parameters ---------- name : str Display / key name for the library entry. uri : str Path or URI to the SPICE model file. Absolute paths, relative paths (resolved from the project directory), and KiCad environment variable references (e.g. ${KICAD_USER_LIB}) are all valid.

Unregister a SPICE model library from the active project file.

Check that registered SPICE libraries are resolvable from the project directory.

Assign a footprint property to a schematic symbol.

Create a simple custom symbol in the active project directory.

Generate a KiCad symbol (.kicad_sym) from a pin table and save it. Each pin dict must contain: ``number`` (str | int), ``name`` (str). Optional per-pin keys: ``pin_type`` (input/output/bidirectional/passive/power_in/power_out/…), ``side`` (left/right/top/bottom), ``unit`` (int ≥ 1). Args: name: Symbol name, used as both the library entry and the default value. pins: List of pin specification dicts. reference_prefix: Ref-des prefix (U, J, Q, R, …). description: Short human description. datasheet: Datasheet URL or path. footprint_hint: Default footprint (e.g. "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"). output_path: Optional relative path inside output_dir. Defaults to ``symbols/<name>.kicad_sym``. Returns: Confirmation with the saved file path, or an error message.

List all embedded (project-embedded) files in the active project. Returns a JSON array of embedded file entries with their metadata (name, source path, description).

Embed an external file into the KiCad project as project metadata. The file content is stored inline inside the ``.kicad_pro`` JSON. Large files (over 1 MB) are rejected to keep project files manageable. Parameters ---------- source_path : str Absolute or relative path to the file to embed. target_name : str | None Name to store the file as (defaults to the source file name). description : str Optional human description of the embedded file.

Extract an embedded file from the project and write it to disk. Parameters ---------- name : str Name of the embedded file to extract (see ``project_list_embedded_files``). output_path : str | None Destination file path. If omitted, extracts to the project directory using the embedded file name.

Remove an embedded file entry from the project metadata. Parameters ---------- name : str Name of the embedded file to remove.

Return the next high-priority action derived from the current project gate.

Initialize a Git repository for the KiCad project directory.

Commit the current project state as a named checkpoint.

List checkpoint commits created by the MCP tool.

Restore project files and keep a recovery branch for the stashed pre-restore state.

Show the current project diff versus a checkpoint commit.

Create an annotated release tag after the full project quality gate passes.

Connect placed-symbol pins to nets with a short outward wire stub plus a terminal placed clear of the symbol body (avoids label-on-pin overlap). Each connection is ``{"reference": "U3", "pin": "VIN" | "5", "net": "5V_SYS"}``; the pin may be a number or a name. The stub direction is derived from the symbol edge the pin sits on, so the terminal lands outside the symbol and reads outward. Power nets get conventional power symbols; other nets get labels. Pins that share a ``net`` are joined by their common terminal name. This is the clean alternative to placing bare labels directly on pins. ``label_kind`` selects the emitted label type for non-power nets: ``"local"``, ``"global"``, or ``"hierarchical"``. When set it takes precedence over the legacy ``global_labels`` boolean, enabling batch placement of hierarchical labels at sheet boundaries. A hierarchical connection may add an optional ``"shape"`` (e.g. ``"input"``, ``"output"``, ``"bidirectional"``) passed through to the label.

Route deterministic Manhattan wire segments between two placed symbol pins.

Insert missing schematic junctions at T-intersection wire endpoints.

List recently opened KiCad projects from KiCad's config files.

Scan a directory and report any KiCad project files it contains.

Return the estimated bounding box of every symbol in the active schematic. Use this before calling sch_add_symbol or sch_build_circuit to understand which areas of the schematic sheet are already occupied. The bounding boxes are heuristic estimates (KiCad does not expose exact extents via the file API) but are conservative enough to avoid overlap in practice. Returns: A table of all symbols with their centre position and estimated bounding-box corners (x_min, y_min, x_max, y_max) in mm, plus an occupied-area summary.

Find N collision-free placement coordinates for new symbols. Reads the current schematic, builds an occupancy grid from all existing symbols, and returns ``count`` coordinate pairs that do not overlap with any placed symbol. Call this before sch_add_symbol to get safe (x, y) values. Args: count: Number of free coordinate slots to return (default 1, max 64). cell_width_mm: Grid cell width in mm (default 25.4 — one 10-mil grid unit). cell_height_mm: Grid cell height in mm (default 17.78). keepout_regions: Optional rectangular keepouts as ``[(x_min, y_min, x_max, y_max), ...]`` in mm. Returns: A list of (x_mm, y_mm) coordinate pairs, one per requested slot.

Register a test-point assignment for a net. Test points are stored as project-sidecar metadata and are applied during the manufacturing release flow. Parameters ---------- net_name : str Target net name (e.g. ``GND``, ``+3V3``). x_mm : float X coordinate in mm. y_mm : float Y coordinate in mm. diameter_mm : float Pad diameter in mm (default 1.0).

List all registered test points for the active project.

Suggest optimal positions for test points on each registered net. Uses the board layout to find accessible pads/vias per net and scores them as candidate test points.

Calculate test-point coverage: how many nets have test points assigned. Compares registered test points against all board nets.

Add a schematic symbol at an absolute coordinate. Coordinates snap to the 1.27 mm / 50 mil schematic grid by default; set snap_to_grid=False only when an exact off-grid coordinate is intentional.

Add a schematic component through the hybrid IPC reload path.

Add a schematic wire, snapping endpoints to the 1.27 mm / 50 mil grid by default.

Add a schematic label, snapping its anchor to the 1.27 mm / 50 mil grid by default. ``justify`` overrides KiCad's centered default (e.g. "left", "right", "top", "bottom", "left top"); local labels have no directional icon so centered text is usually correct and this is rarely needed.

Add a power symbol, snapping its anchor to the 1.27 mm / 50 mil grid by default.

Add a schematic bus, snapping endpoints to the 1.27 mm / 50 mil grid by default.

Add a bus wire entry marker. Snaps its anchor to the 1.27 mm / 50 mil grid by default.

Add a no-connect marker, snapping it to the 1.27 mm / 50 mil grid by default.

Place many labels in one call, snapping each to the 1.27 mm / 50 mil grid. Each ``labels`` entry is a dict: ``name``, ``x_mm``, ``y_mm`` and optional ``rotation``, ``kind`` ("local"|"global"|"hierarchical"; default "local"), ``shape`` (for hierarchical/global labels), ``justify`` and ``snap_to_grid``. An invalid ``kind`` names the offending entry index.

Update a property on a placed symbol.

Set KiCad's native Do Not Populate flag on a placed symbol. When ``reason`` is given it is stored in the ``DNP Reason`` property so ``sch_get_population_status`` and variant BOMs can report why the part is unpopulated.

Modify a schematic symbol property by reference.

Move an existing symbol instance to a new absolute coordinate.

Begin a transaction group for atomic board modifications. All subsequent mutations (add, remove, update operations) will be grouped into a single undo step in KiCad. Call pcb_push_commit to apply or pcb_drop_commit to discard. Returns: Confirmation message with commit status.

Push (commit) the current transaction group to the board. All mutations since pcb_begin_commit will be applied as a single undo step. Returns: Confirmation message with commit status.

Drop (discard) the current transaction group without applying changes. All mutations since pcb_begin_commit will be discarded. Returns: Confirmation message with drop status.

Revert the board to the last saved state, discarding all unsaved changes. WARNING: This is a destructive operation. All unsaved modifications will be lost. Returns: Confirmation message with revert status.

Return sanitized native-live PCB transaction state as deterministic JSON.

Export the PCB to a 3D PDF. Parameters ---------- output_path : str Output file name (relative to the export output directory).

Report configured solver-grade analysis capabilities and unavailable seams.

Estimate PCB trace impedance using quasi-static interconnect formulas.

Solve for a trace width that meets the requested impedance target.

Estimate differential-pair length skew and delay mismatch from board tracks. Returns a PASS/WARN/FAIL verdict. The skew budget comes from ``skew_budget_ps`` if > 0, otherwise from the matching design-intent interface, otherwise a conservative default. PASS within budget, WARN up to 2x budget, FAIL beyond.

Validate that each net group is matched within the supplied tolerance.

Estimate high-speed channel insertion loss and eye opening for a lossy trace. Sums conductor skin-effect and dielectric (tan-delta) loss to get insertion loss at the Nyquist rate, then a first-order loss-limited eye height, with a PASS/WARN/FAIL verdict against ``max_insertion_loss_db``. When an ngspice CLI is available the insertion loss is measured from an RLGC-ladder AC sweep; otherwise a closed-form estimate is used. The method label states which path produced the numbers.

Generate a practical board stackup recommendation and target trace geometry.

Estimate via-stub resonance and risk for selected vias on the active board. ``via_positions`` are ``[x_mm, y_mm]`` two-element arrays.

Estimate decoupling placement quality around an IC power pin.

List all built-in dielectric materials with Er, loss tangent, and frequency range. Use the returned material keys with si_synthesize_stackup_for_interfaces() to select the appropriate laminate for your design.

Synthesise a PCB stackup that meets the impedance requirements of the given interfaces. Analyses each InterfaceSpec dict and recommends: - Layer count - Dielectric material - Copper weight per layer - Outer dielectric thickness for target impedance - Net class settings (impedance, clearance, diff-pair gap) Args: interfaces: List of InterfaceSpec dicts (matching project_set_design_intent interface format). Each must have at least ``kind`` and optionally ``impedance_target_ohm``, ``differential``, ``diff_skew_max_ps``. cost_tier: ``"standard"`` (FR4), ``"midloss"`` (FR4 mid/low-loss), ``"highspeed"`` (Rogers/Megtron). Overrides material selection. board_thickness_mm: Target board thickness in mm (1.0, 1.6, 2.0, 3.2). Returns: Recommended stackup specification and net class table in human-readable markdown, ready to pass to pcb_set_stackup() and pcb_set_net_class().

Map interface specs from the project design intent to KiCad net classes. For each interface with an impedance target, this tool generates the pcb_set_net_class() calls needed to enforce clearance and diff-pair rules. When ``dry_run=True`` (default), only returns the plan without executing it. Args: interfaces: List of InterfaceSpec dicts from project_get_design_spec(). dry_run: If True, return the mapping plan without modifying the project. Set to False to have the tool call pcb_set_net_class() for each class. Returns: Net class plan or confirmation of changes applied.

List all DRC violation exclusions stored for the active project. Returns a JSON array of exclusions, each with a 'uuid' (violation identifier), 'reason', and 'created' timestamp.

Add DRC exclusions for the current violation set. Runs DRC, lists all violations, and asks the user to pick which UUIDs to exclude. Because MCP tools cannot interactively prompt, this tool excludes ALL current DRC violations and records a reason string. Use ``drc_list_exclusions`` afterward to review what was excluded.

Remove a single DRC exclusion by its violation UUID. Use ``drc_list_exclusions`` to retrieve the UUID of the exclusion to remove.

Validate that stored DRC exclusions still cover active violations. Re-runs DRC and reports which previously excluded violations are still present (valid) and which have been resolved (stale).

List known ERC rules and their current severity levels. Severity levels are: ``error``, ``warning``, or ``ignore``.

Override the severity of an ERC rule. Parameters ---------- rule_name : str Name of the ERC rule (use ``erc_list_rules`` to see available names). severity : str One of ``error``, ``warning``, or ``ignore``.

Reset one or all ERC rule severities back to their default (``error``). Parameters ---------- rule_name : str | None Specific rule to reset, or omit to reset all rules.

Create a new minimal KiCad project structure and activate it.

Export a KiCad schematic netlist.

Export a SPICE netlist.

Capture the current render of a schematic sheet as its visual baseline. Renders the sheet headlessly and stores the PNG plus metadata (dpi, source hash) under ``.kicad-mcp/visual_baselines/``. Call this once a sheet looks right; ``sch_visual_baseline_compare`` then flags any later visual drift.

Compare a sheet's current render against its stored visual baseline. Renders the sheet, diffs it pixel-wise against the baseline, and reports the drift percentage, the changed bounding box, and a highlighted diff image. Status is ``PASS`` when drift is within ``threshold_pct``, else ``DRIFT``. Reports ``no_baseline`` if the sheet was never captured.

Export pick and place (CPL) data for the active PCB. Parameters ---------- format : str Output format (e.g. ``csv``, ``ascii``). variant : str | None Optional design variant name. When set, exports variant-specific pick-and-place data (component population, value, footprint overrides). Uses the active variant when omitted.

Export the active PCB to IPC-2581 format.

Export the active PCB to ODB++ format.

Estimate trace impedance for the supplied width on the named stackup layer.

Run a heuristic creepage clearance review against pad spacing.

Report currently unconnected board items using the latest DRC view.

Read the active board design rules file when available.

Write board-level manufacturing constraints into the active .kicad_dru file.

Add a single track segment.

Route a trace segment through the KiCad IPC-backed track tool.

Add multiple tracks in a single operation.

Add a via.

Add a blind or buried via between the requested copper layers.

Add a microvia between adjacent copper layers.

Add a board graphic segment.

Add a board graphic circle.

Add a board graphic rectangle.

Draw a rectangular board outline on Edge.Cuts.

Add board text.

Add a production barcode marker to the board file using KiCad's native barcode format.

Import a bitmap/logo as deterministic board-art rectangles on a PCB layer.

Delete items by UUID.

Delete a single PCB object by UUID through KiCad IPC.

Save the active board.

Refill all copper zones.

Attempt to highlight a net in the GUI when supported.

Assign a net class when the runtime supports it.

Place an already-synced PCB component at an absolute location.

Move a PCB component by reference using the live footprint operation.

Move a footprint to an absolute location.

Set the footprint copper side.

Inject an inner-layer graphic primitive into a footprint block.

Sync missing PCB footprints from schematic footprint assignments. This is a file-based operation intended for initial board bring-up. It adds missing footprint instances to the `.kicad_pcb` file using schematic references, values, rotations, and assigned `Library:Footprint` names. When `replace_mismatched=True`, existing footprints with the same reference but the wrong footprint name are replaced in place.

Place PCB footprints from the current schematic using deterministic heuristics.

Move capacitor footprints into a tight row near a target IC footprint.

Cluster existing footprints into named functional groups.

Arrange selected footprints into a straight row or column.

Add a copper zone with an arbitrary polygon outline on one copper layer.

Backward-compatible alias for pcb_add_zone().

Add a rectangular PCB keepout / rule area to the active board.

Append standard mounting-hole footprints around the current board frame.

Append simple fiducial footprints near the board corners.

List stored PCB design blocks created from selected footprints.

Capture a reusable PCB design block from selected footprint references.

Place a stored PCB design block by cloning its saved footprint blocks.

Create small copper helper zones at simple pad-to-track junctions.

Run a force-directed spring-embedder placement algorithm on a set of components. This tool computes optimised X/Y positions for components based on their net connectivity without requiring KiCad to be open. Stopping is deterministic: iteration halts on convergence (or the ``iterations`` ceiling), never on wall-clock, so the same seed + same inputs yield bit-for-bit identical output on any machine. Use it to get a placement suggestion, then apply the result with pcb_move_footprint for each component. Args: component_positions: List of component dicts with keys: ref (str), x (float, mm), y (float, mm), w (float, mm, optional default 2), h (float, mm, optional default 2), fixed (bool, optional default false). nets: List of net dicts with keys: name (str), refs (list[str]), weight (float, optional default 1.0). board_width_mm: Soft boundary width in mm (default 100). board_height_mm: Soft boundary height in mm (default 80). iterations: Number of spring-embedder iterations (default 300). k_spring: Spring attraction coefficient (default 0.4). k_repel: Coulomb repulsion coefficient (default 80.0). seed: Deterministic tie-break seed used for fallback searches. grid_mm: Final snap-to-grid spacing in mm (default 0.5). max_seconds: Opt-in wall-clock safety valve in seconds. 0 (default) keeps placement deterministic and convergence-bounded; a positive value caps runtime on pathologically large boards but makes the result depend on host speed (not reproducible). keepout_regions: Optional rectangular keepouts as ``[[x_min, y_min, x_max, y_max], ...]`` in mm. Returns: JSON string with optimised positions for each component.

Generate a BGA fanout via-placement plan (dog-ear or inline strategy). Returns per-ball via coordinates and suggested track widths so the agent can call pcb_add_via and pcb_add_track to physically fanout the BGA. Actual pad coordinates must come from the board footprint (use pcb_get_pads). Args: balls: List of ball dicts with keys: row (str, e.g. "A"), col (int, 1-based), net (str), x_mm (float, ball centre X), y_mm (float, ball centre Y). pitch_mm: Ball pitch in mm (e.g. 0.5, 0.65, 0.8, 1.0). via_drill_mm: Via drill diameter in mm (default 0.2). via_annular_mm: Via annular ring width in mm (default 0.1). escape_layer: Inner copper layer to fan out to (default "In1.Cu"). strategy: "dog_ear" (diagonal escape, most common) or "inline" (horizontal escape, for large pitch). Returns: JSON string with via placement plan for each ball.

Analyse PCB component placement for common design-quality issues. Runs four constraint-driven rules against the active board file: - **PLR-001** Decoupling-cap-to-IC distance — bypass caps should be ≤ ``max_decap_distance_mm`` mm from the IC they serve. - **PLR-002** Crystal-to-IC distance — oscillator crystals should be ≤ ``max_crystal_distance_mm`` mm from the companion MCU/IC. - **PLR-003** SMPS hot-loop area — the bounding box of a switching IC, its inductor, and nearby caps should not exceed ``max_smps_loop_area_mm2`` mm². - **PLR-004** Analog / digital region mixing — components carrying AGND / AVCC nets should not co-mingle with digital-supply components within ``analog_digital_separation_mm`` mm. Returns a JSON summary with per-rule findings and an overall verdict.

List all available reference subcircuit templates. Templates are pre-wired subcircuit blueprints for common building blocks (buck converter, LDO, USB Type-C, MCU decoupling, Ethernet with magnetics). Call sch_get_template_info() for full parameter and placement details, then sch_instantiate_template() to add the subcircuit to the schematic.

Return full details for a subcircuit template. Args: template_name: Template name as returned by sch_list_templates() (e.g. ``"buck_converter_generic"``). Returns: Structured template description including parameters, symbols, nets, and placement hints.

Export board statistics and return a readable preview.

Export board statistics (net count, component count, layer count, etc.) via the KiCad CLI ``pcb export stats`` command. Parameters ---------- output_name : str | None Optional output file name (saved under the project output directory). Defaults to ``board_stats.json``.

Estimate DC voltage drop, trace resistance, and IPC-2221 current-density fusing. ``max_temp_rise_c`` is the temperature-rise budget; the verdict is PASS within it, WARN up to 2x, FAIL beyond. Set ``internal_layer=True`` for a buried trace (lower ampacity).

Run a lightweight PDN mesh voltage-drop check for a power net.

Recommend local and bulk decoupling from a simple PDN heuristic.

Check whether the routed copper for a net looks sufficient for the load current.

Generate a rectangular copper plane on the requested copper layer.

Estimate thermal via count from package heat and board thermal resistance.

Check whether the board already has copper pour support for the net.

Solve copper-plane heat spreading with a 2-D finite-difference thermal solver. Models a hot source dissipating ``power_w`` into a copper plane that loses heat to ambient through both faces (``film_coefficient_w_per_m2_k`` is the combined top+bottom film coefficient). Returns the peak and average temperature rise from a genuine distributed steady-state solve, with a PASS/WARN/FAIL verdict against ``max_temp_rise_c``. This is a 2-D spreading solve, not a 3-D FEA with airflow.

Return versioned server information and capability diagnostics for clients.

Update the active IDE context pushed by KiCad Studio.

Search KiCad documentation and knowledge base for PCB design topics.

Analyze an uploaded KiCad project archive.

Interpret a DRC (Design Rule Check) report and explain issues.

Interpret an ERC (Electrical Rule Check) report and explain issues.

Generate a manufacturing readiness report for a KiCad project.

Generate an MCP configuration snippet for a supported AI coding agent.